[SSC] Seminar! - Circuit Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs

Mon Oct 23 22:26:36 IRST 2006

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  Circuit Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs

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  Carbon Nanotube Field Effect Transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance is determined by the angle of atom arrangement along the tube called chirality. It is difficult to control chirality during manufacturing. This causes conducting (metallic) nanotubes as well as defective CNTFETs similar to stuck-on (source-drain short) faults, as encountered in classical MOS devices. Our research studies this phenomenon by using layout information and presents modeling and detection methodologies for nano-scaled defects arising from the presence of metallic carbon nanotubes. For CNTFET-based circuits (e.g. intra-molecular), these defects are represented using a traditional stuck-at fault model. This analysis is applicable to primitive and complex gates. Simulation results are presented for detecting modeled metallic nanotube faults in CNTFETs
 using a single stuck-at fault test set. On average, the proposed technique achieves defect coverage of 98% over 18 different benchmark circuits.

    Hamidreza Hashempour received B.Sc. and M.Sc. degrees in computer engineering from the Fanni Faculty of the Tehran  University and Ph.D. degree from Northeastern  University. He was a visiting research associate of nanotechnology at Northeastern  University working on Quantum Cellular Automata (QCA) clocking integrity and computationally efficient simulation of nano-scaled devices.

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